One known nonvolatile semiconductor memory is a NAND flash memory. In a NAND flash memory, when data is read or verified, specific potentials are applied to the source of a memory cell and a well region in which the memory cell has been formed. Various methods of arranging metal interconnection layers for applying the potentials have been proposed. One of the propositions has been disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2009-033099. It is desirable that the interconnections should be arranged so that the interconnection resistance (parasitic resistance) may be minimized. In this respect, when the length of the metal interconnection layer becomes longer, the effect of the interconnection resistance can increase to the degree that it is not negligible, which might lead to erroneous reading or writing.
In addition, when data is read, it is necessary to apply a specific potential to the source line through a MOS transistor. In this case, if the gate-source voltage of the MOS transistor is close to its threshold value, the operation of the MOS transistor becomes unstable, which might result in a decrease in the reading accuracy.